Random Access Memory (RAM)

 

SRAM (Static RAM):

SRAM is a type of RAM that holds data, placed within its cells, until the values are either overwritten or the power is removed. This is opposed to Dynamic RAM (DRAM), which allows the data to exit  by the cells discharging, every few milliseconds unless it is refreshed.

 In static RAM, a form of flip-flop holds each bit of memory. A flip-flop for a memory cell usually takes four or six transistors, but never has to be refreshed. This makes static RAM significantly faster, with access times in the 10 to 30-nanosecond range,  than DRAM. However, because it has more parts, a static memory cell takes up  more space on a chip than a dynamic memory cell. Therefore, you get less memory per chip, which makes static RAM  more expensive.

The circuit schematic shown below utilises bipolar dual emitter devices:

 

In STANDBY MODE the cell select line is held at a lower potential (0.3 Volts) than the DATA or /DATA lines (1 to 2 Volts). So current goes through the cell select line from the ON transistor and DATA and /DATA lines are in high impedance state.

To READ data the cell select line is raised high (3 Volts) and DATA and /DATA lines are fed to a differential amplifier which gives a high or low out, depending on the state of T1 and T2.

To WRITE data the cell select line is raised high (3 Volts) and then either the DATA or  /DATA line is lowered to 0 Volts to write a 1 or a 0 into the cell.

So static RAM is fast and expensive, and dynamic RAM is less expensive and slower. Generally static RAM is used to create the CPU's speed-sensitive cache, while dynamic RAM forms the larger system RAM space.

 

DRAM (Dynamic RAM):

Just like static RAMs, the memory on a dynamic RAM memory chip is organized in a matrix formed by rows and columns of memory cells. The simplest type of dynamic RAM cell contains only one transistor and one capacitor.  Whether a 1 or 0 is contained in a cell is determined by whether or not there is a charge on the capacitor. During a read operation, one of the row select lines is brought high by decoding the row address (low-order address bits). The activated row select line turns on the switch transistors  for all cells in the selected row. This causes the refresh amplifier associated with each column to sense the voltage level on the corresponding capacitor and interpret it as a 0 or a 1. If it is more than 50 percent, it reads it as a 1; otherwise it reads it as a 0. The column address (high-order address bits) enables one cell in the selected row for the output. The read cycle is actually a read/write cycle. If a '1' is read then the cell is re-written to with a '1' to recharge it. However if a '0' is read no recharge is necessary.

During this process, the capacitors in an entire row are disturbed. In order to retain the stored information, the same row of cells is rewritten by the refresh amplifiers. A write operation is done similarly except that the data input is stored in the selected cell while the other cells in the same row are simply refreshed. As a result of the storage discharge through pn-junction leakage current, dynamic memory cells must be repeatedly read and restored, this process is called memory refresh. The storage discharge rate increases as the operating temperature rises, and the necessary time interval between refreshes ranges from 1 to 100 ms.

The capacitor Cs discharges through the internal resistance of the NMOS transistor T1. Typically Cs = 0.2 pF and the internal resistance Rin = 1010 ohms, so:

Cs x Rin = 0.2 x 10-12  x 1010 x 103  ms   =  2 ms

So the typical refresh time interval is 2 ms. Although a row of cells is refreshed during a read or write, the randomness of memory references cannot guarantee that every word in a memory module is refreshed within the 2-ms time limit. A systematic way of accomplishing a memory refresh is through memory refresh cycles.

 

Memory Refresh Cycle

In a memory refresh cycle, a row address is sent to the memory chips, and a read operation is performed to refresh the selected row of cells. However, a refresh cycle differs from a regular memory read cycle in the following respects:

1. The address input to the memory chips does not come from the address bus. Instead, the row address is supplied by a binary counter called the refresh address counter. This counter is incremented by one for each memory refresh cycle so that it sequences through all the row addresses. The column address is not involved because all elements in a row are refreshed simultaneously.

2. During a memory refresh cycle, all memory chips are enabled so that memory refresh is performed on every chip in the memory module simultaneously. This reduces the number of refresh cycles. In a regular read cycle, at most one row of memory chips is enabled.

3. In addition to the chip enable control input, normally a dynamic RAM has a data output enable control. These two control inputs are combined internally so that the data output is forced to its high-impedance mode unless both control inputs are activated. During a memory refresh cycle, the data output enable control is deactivated. This is necessary because all the chips in the same column are selected and their data outputs are tied together. On the other hand, during a regular memory read cycle, only one row of chips is selected, consequently, the data output enable signal to each row is activated.

 

 The memory cells have a whole support infrastructure of other specialized circuits. These circuits perform functions such as:

* Identifying each row and column (row address select and column address select)
* Keeping track of the refresh sequence (counter)
* Reading and restoring the signal from a cell (sense amplifier)
* Telling a cell whether it should take a charge or not (write enable)

Other functions of the memory controller include a series of tasks that include identifying the type, speed and amount of memory and checking for errors.